1. Field of the Invention
The present invention relates to retriggerable oscillators and more particularly to voltage controlled ring oscillators.
2. Description of the Prior Art
Various kinds of electronic test equipment and circuit analyzers depend upon clocks and other triggers that will signal when to sample a device-under-test (DUT) or when to start/end some other process. The quality of such clocks and triggers is typically dependent on the stability and absence from jitter of a phase locked loop (PLL) that synchronizes a ring oscillator to a main timing reference source. If the range and granularity of the required signals needed were not so stringent, a simple oscillator with a digital counter operating at a high harmonic frequency of the needed fundamental frequencies could be used to generate the required multi-phase signals. But high performance testers must generate a signal or a pair of signals that can be varied with predictable resolutions in period to a few nanoseconds and range from zero to a hundred megahertz (Hz). Therefore multi-stage ring oscillators have been conventionally employed to produce phase shifted signals locked to a reference frequency that can be combined to produce the necessary outputs.
Ghoshal, et al., describe in U.S. Pat. No. 5,077,529, issued Dec. 31, 1991, a wide bandwidth digital phase locked loop (DPLL) with reduced low frequency intrinsic jitter. One of several available taps on a multi-stage ring oscillator is selected by a frequency adjustment circuit that allows any consecutive phase of oscillator to be selected. The selection output is used to clock a DPLL. A high-speed clock may be advanced or retarded by selecting a different phase tap. A reference input clock is input via a phase detector in the DPLL. The high-speed clock is operated at twelve times the DPLL frequency clock to reduce jitter. Ghoshal, et al., claim a reduction of ten times in the low frequency jitter of the DPLL over prior art methods.
Current-controlled ring oscillators in phase lock loops are conventional, as exemplified by the teachings of Giolma, et al., in U.S. Pat. No. 4,091,335, issued May 23, 1978. A ring is comprised of lateral PNP current sources and Schottky clamped NPN transistors to provide a frequency range of four megahertz at fifty microamp drive to forty-three megahertz at one milliamp drive. The frequency of the ring oscillator is varied by adjusting the current injected into the ring. Such ring oscillators require less chip area to implement and less frequency error to produce correction. Therefore, ring oscillators can suffer from less jitter.
A PLL configured as a frequency multiplier capable of non-integral feedback path division is described by JenningsCheck in U.S. Pat. No. 5,059,924, issued Oct. 22, 1991. A multiphase voltage controlled oscillator (VCO) generates a plurality of signals 10a-10f having substantially identical frequency but each are offset equally from the next by a given phase angle. A commutator selects signals of adjacent phases for a time average output signal with a frequency higher or lower than signals 10a-10f. Frequency translation is done by periodically selecting signals having a longer or shorter period as desired so the output signal is delayed or advanced by the appropriate amount. Such a PLL is capable of converting a. 1.544 MHz signal to a 2.048 MHz signal, and vice versa, and which are not integer multiples of the other, as would otherwise be necessary with a conventional VCO.
U.S. Pat. No. 4,902,986, issued Feb. 20, 1990, to the present inventor, Gary Lesmeister, describes a PLL for precise frequency and phase tracking of two signals that are calibrated to an external reference signal. Such patent is incorporated herein by reference as if fully laid out. An implementation is described which is suitable for inclusion into an integrated circuit (IC). The device comprises a ring oscillator for generating a calibration signal that oscillates at a first frequency and a power supply for sourcing a compensated power signal to the ring oscillator. The first frequency is variable based on the voltage of the compensated power signal. A phase detector is used to detect a relative phase between the calibration signal and the external reference signal. The compensated power signal is also used for critical data paths within the IC where precise timing is required. In a tester, a plurality of signals are extracted from the ring oscillator with a multitude of taps that have signals which oscillate at the same frequency as the calibration signal but each of which differ from it by different phase angles. Such difference in phase angle will be equal to 360.degree. divided by the number of stages (N) in the ring oscillator. The signals from the taps are combined in multiplexers to form test signals that can be applied to a device-under-test (DUT). Thirty-one stages are shown in FIG. 5 of the subject patent, yielding 360.degree. /31, or 11.6.degree. of phase shift per stage.
FIG. 1 illustrates a PLL 10 with a ring oscillator 12 made up of an odd number (N) of ring of inverters 14 and a combination phase detector and charge pump 16 that maintains a phase lock of the ring oscillator 12 to a signal input from a reference oscillator (ROSC) 18. A timing path 20 with an associated delay allows the ring oscillator 12 to lead. ROSC 18 in phase to compensate for timing edge generator and other unavoidable logic delays. An amplifier 22 powers the ring oscillator 12 with a voltage VPLL that will adjust the transition delays of each inverter 14 such that the total of all the delays in the ring add up to the period of the ROSC 18. The ring oscillator 12 oscillates at the same frequency as the ROSC 18 as long as the ROSC 18 is within the lock range of the PLL 10. Prior art testers and associated ICs use such configurations to eliminate CMOS process and temperature effects that are detrimental to stable time generation. The ring oscillator 12 is frequency-locked but not directly coupled to the ROSC 18. Therefore, the ring oscillator 12 may be phase shifted to compensate for the undesirable effects of process and temperature variances in certain critical timing paths. However, the phase shifting configuration exacerbates higher frequency jitter effects. In modern high-performance testers, such jitter cannot be tolerated, but neither can expensive remedies.
Prior art attempts to control jitter have resorted to various filters and external components. A voltage follower and filter external to a tester IC were discovered by the present inventor to offer some of the stability needed for a high-performance system, but the resulting jitter was nevertheless still within the upper limits of what is acceptable. So such a system is limited in period agility.
A conventional tester IC timebase 24 is shown in FIG. 2. A reference signal from a ROSC 25 is loosely coupled to a clock and a plurality of timing edge generator (TEG) signals from a ring oscillator 26 through a PLL control voltage (VPLL). Such a loose coupling allows the outputs of ring oscillator 26 to accumulate undesirable phase errors until a correction to VPLL can respond through a loop delay equal to the phase error of ROSC to t.sub.0fx. The phase error varies with time and appears as phase jitter with respect to ROSC 25. The ring oscillator 26 allows a multitude of taps, equal to the number N of elements in the ring oscillator, to sample ROSC 25 at N number of phase delays. The phase delay time between adjacent taps separated by one ring element is the inverse of "N" times ROSC. A synthesized frequency may be generated by selecting one tap and then another separated in phase by a time equal the period of the desired frequency to be synthesized. A plurality of timing edge generators 27 are used to implement such tap selection in real time. For example, with ROSC 25 equal to fifty MHz, the ring oscillator period will be twenty picoseconds. If there were twenty elements to the ring oscillator, each with a delay of two picoseconds, frequencies with periods only two picoseconds apart could be synthesized by appropriate tap selection. A phase lock loop 28 varies a voltage VPLL to keep the ring element delays at precisely two picoseconds. But, variations in semiconductor fabrication processes and temperatures will conspire to throw the frequency of ring oscillator 26 off its target.
A variability in the frequency of ROSC 25 allows a 5 testing system to be constructed that can generate synthesized frequencies having periods from twenty to forty picoseconds in very small increments. But since the number of taps on the ring is fixed, the resolution at twenty-five MHz is forty picoseconds compared to twenty picoseconds at fifty MHz. Therefore, the synthesizable frequency granularity can degrade dramatically when changing reference frequencies, for example fifty MHz to twenty-five MHz.
In the prior art, VCO spanning requirements of a 2:1 frequency range will necessarily limit the stability of a PLL. Changing the reference period in such a case will also complicate calculations for a target synthesized frequency. Furthermore, timing noise and errors will typically increase as ROSC approaches twenty-five MHz. At twenty-five MHz, the timing path delay is more than doubled, thus decreasing performance and accuracy, and that increases the complexity of the circuitry. Since ROSC is loosely coupled to the clock and the timing edge generator (TEG) signals from the RING through VPLL, this loose coupling means the RING outputs will accumulate undesirable phase errors, imposed by environmental changes, until VPLL responds via the loop delay with respect to the ROSC to t.sub.0fx phase error. This phase error varies with time and appears as phase jitter with respect to ROSC.